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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
January 2007
FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Features
8 x 6 Crosspoint Switch Matrix Supports SD, PS, and HD 1080i / 1080p Video Input Clamp and Bias Circuitry Doubly Terminated 75 Cable Drivers Programmable 0dB or 6dB Gain AC- or DC-Coupled Inputs AC- or DC-Coupled Outputs One-to-One or One-to-Many Input-to-Output
Description
The FMS6502 provides eight inputs that can be routed to any of six outputs. Each input can be routed to one or more outputs, but only one input may be routed to any output. Each input supports an integrated clamp option to set the output sync tip level of video with sync to ~300mV. Alternatively, the input may be internally biased to center output signals without sync (Chroma, Pb, Pr) at ~1.25V. All outputs are designed to drive a 150 DC-coupled load. Each output can be programmed to provide either 0dB or 6dB of signal gain. Input-to-output routing and input bias mode functions are controlled via an I2C-compatible digital interface.
Switching I2CTM-Compatible Digital Interface, Standard Mode 3.3V or 5V Single Supply Operation Pb-Free TSSOP-24 Package
Applications
Cable and Satellite Set-Top Boxes TV and HDTV Sets A / V Switchers Personal Video Recorders (PVR) Security and Surveillance Video Distribution Automotive (In-Cabin Entertainment)
Block Diagram
IN1 C/B
IN2
C/B
IN8
C/B
SDA SCL ADDR0 ADDR1 VCC (2) GND (4) OUT1 OUT2 OUT6
Figure 1. Block Diagram
Ordering Information
Part Number
FMS6502MTC24 FMS6502MTC24X
Pb-Free
Yes Yes
Operating Temperature Range
-40C to 85C -40C to 85C
Package
24-Lead Thin Shrink Small Ouline Package 24-Lead Thin Shrink Small Ouline Package
Packing Method
Rail Reel
(c) 2006 Fairchild Semiconductor Corporation Rev. 1.0.0
www.fairchildsemi.com
FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Pin Configuration
Pin Description
Pin#
1 2 3
22
IN1 GND IN2 VDD IN3 GND IN4 ADDR1 IN5 ADDR0 IN6 SCL
1 2
24 23
GND OUT1 OUT2 OUT3 VDD OUT4 OUT5 OUT6 GND IN8 SDA IN7
Pin
IN1 GND IN2 VDD IN3 GND IN4 ADDR1 IN5 ADDR0 IN6 SCL IN7 SDA IN8 GND OUT6 OUT5 OUT4 VDD OUT3 OUT2 OUT1 GND
Type
Input Output Input Input Input Output Input Input Input Input Input Input Input Input Input Output Output Output Output Input Output Output Output Output
Description
Input, channel 1 Must be tied to ground Input, channel 2 Positive power supply Input, channel 3 Must be tied to ground Input, channel 4 Selects I2C address Input, channel 5 Selects I2C address Input, channel 6 Serial clock for I2C port Input, channel 7 Serial data for I2C port Input, channel 8 Must be tied to ground Output, channel 6 Output, channel 5 Output, channel 4 Positive power supply Output, channel 3 Output, channel 2 Output, channel 1 Must be tied to ground
FAIRCHILD
3
FMS6502
4 21
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
24L TSSOP
5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13
Figure 2. Pin Configuration
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Parameter
DC Supply Voltage Analog and Digital I/O Output Current Any One Channel, Do Not Exceed
Min.
-0.3 -0.3
Max.
6 Vcc + 0.3 40
Unit
V V mA
Reliability Information
Symbol
TJ TSTG TL JA Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Thermal Resistance, JEDEC Standard Multi-Layer Test Boards, Still Air 84 -65
Parameter
Min.
Typ.
Max.
150 150 300
Unit
C C C C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA VCC Supply Voltage Range
Parameter
Operating Temperature Range
Min.
-40 3.135
Typ.
5.0
Max.
85 5.25
Unit
C V
Electrostatic Discharge Information
Symbol
HBM CDM
Parameter
Human Body Model (JEDEC: JESD22-A114) Charged Device Model (JEDEC: JESD22-A101)
Value
10 2
Unit
kV kV
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
www.fairchildsemi.com 3
FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Digital Interface
The I2C-compatibe interface is used to program output enables, input-to-output routing, and input bias configuration. The I2C address of the FMS6502 is 0x06 (0000 0110) with the ability to offset based upon the values of the ADDR0 and ADDR1 inputs. Offset addresses are defined below:
ADDR1
0 0 1 1
ADDR0
0 1 0 1
Binary
0000 0110 0100 0110 1000 0110 1100 0110
Hex
0x06 0x46 0x86 0xC6
Data and address data of eight bits each are written to the FMS6502 I2C address register to access control functions. For efficiency, a single data register is shared between two outputs for input selection. More than one output can select the same input channel for one-to-many routing.
The clamp / bias control bits are written to their own internal address since they should remain the same regardless of signal routing. They are set based on the input signal that is connected to the FMS6502. All undefined addresses may be written without effect.
Output Control Register Contents and Defaults Control Name
In-A In-B
Width
4 bits 4 bits
Type
Write Write
Default
0 0
Bit(s)
3:0 7:4
Description
Input selected to drive this output: 0000=OFF1, 0001=IN1, 0010=IN2, 1000=IN8 Input selected to drive this output: 0000=OFF1, 0001=IN1, 0010=IN2, 1000=IN8
Output Control Register MAP Name
OUT1,2 OUT3,4 OUT5,6
Address
0x00 0x01 0x02
Bit 7
Bit 6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
B3-Out2 B2-Out2 B1-Out2 B0-Out2 B3-Out1 B2-Out1 B1-Out1 B0-Out1 B3-Out4 B2-Out4 B1-Out4 B0-Out4 B3-Out3 B2-Out3 B1-Out3 B0-Out3 B3-Out6 B2-Out6 B1-Out6 B0-Out6 B3-Out5 B2-Out5 B1-Out5 B0-Out5
Clamp Control Register Contents and Defaults Control Name
Clmp
Width
1 bit
Type
Write
Default
0
Bit(s)
7:0
Description
Clamp / Bias selection: 1 = Clamp, 0 = Bias
Clamp Control Register Map Name
CLAMP
Address
0x03
Bit 7
Clmp8
Bit 6
Clmp7
Bit5
Clmp6
Bit4
Clmp5
Bit3
Clmp4
Bit2
Clmp3
Bit1
Clmp2
Bit0
Clmp1
Gain Control Register Contents and Defaults Control Name
Gain
Width
1 bit
Type
Write
Default
0
Bit(s)
7:0
Description
Output Gain selection: 0 = 6dB, 1 = 0dB
Gain Control Register Map Name
GAIN
Address
0x04
Bit 7
Unused
Bit 6
Unused
Bit5
Gain6
Bit4
Gain5
Bit3
Gain4
Bit2
Gain3
Bit1
Gain2
Bit0
Gain1
Note: 1. When the OFF input selection is used, the output amplifier is powered down and enters a high-impedance state.
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
DC Electrical Characteristics
TA = 25C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC-coupled with 0.1F, unused inputs AC-terminated through 75 to GND, all outputs AC-coupled with 220F into 150, referenced to 400kHz unless otherwise noted.
Symbol
ICC VOUT Vclamp
Parameter
Supply Current(1) Video Output Range DC Input Level
(1) (1)
Conditions
No Load, All Outputs Enabled Clamp Mode, All Gain Settings Clamp Mode, 0dB Gain Setting Clamp Mode, 6dB Gain Setting Bias Mode, All Gain Settings Bias Mode, 0dB Gain Setting Bias Mode, 6dB Gain Setting
Min.
Typ.
55 2.8
Max.
75 0.20 0.20 0.40 0.675 0.700 1.400
Unit
mA Vpp V V V V V V dB
0.10 0.10 0.20 0.575 0.575 1.150
0.15 0.15 0.30 0.625 0.625 1.250 90
DC Output Level DC Input Level
DC Output Level(1)
(1) (1) (1)
Vbias PSRR
DC Output Level DC Output Level
Power Supply Rejection Ratio All Channels, DC
Note: 1. 100% tested at 25C.
AC Electrical Characteristics
TA= 25C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC-coupled with 0.1F, unused inputs AC-terminated through 75 to GND, all outputs AC-coupled with 220F into 150, referenced to 400kHz unless otherwise noted.
Symbol
AV0dB AV6dB f+1dB f-1dB fC dG d THDSD THDHD XTALK1 XTALK2 XTALK3 XTALK4 XTALK5 SNRSD VNOISE AMPON
Parameter
Channel Channel Gain(1) Gain(1)
Conditions
DC, All Channels, 0dB Gain Setting DC, All Channels, 6dB Gain Setting VOUT = 1.4Vpp VOUT = 1.4Vpp VOUT = 1.4Vpp VCC = 5.0V , 3.58MHz VCC = 5.0V , 3.58MHz VOUT = 1.4Vpp, 5MHz, VCC = 5.0V VOUT = 1.4Vpp, 22MHz, VCC = 5.0V 1MHz, VOUT = 2Vpp(2) 15MHz, VOUT = 2Vpp(2) 1MHz, VOUT = 2Vpp(3) 15MHz, VOUT = 2Vpp(3) Standard Video, VOUT = 2Vpp
(4) (5)
Min.
-0.2 5.8
Typ.
0 6 65 90 115 0.1 0.2 0.05 0.4 -77 -62 -81 -62 -50 78 20 300
Max.
+0.2 6.2
Unit
dB dB MHz MHz MHz % % % dB dB dB dB dB dB
+1dB Peaking Bandwidth -1dB Bandwidth -3dB Bandwidth Differential Gain Differential Phase SD Output Distortion HD Output Distortion Input Crosstalk Input Crosstalk Output Crosstalk Output Crosstalk Multi-Channel Crosstalk Signal-to-Noise Ratio Channel Noise Amplifier Recovery Time
NTC-7 Weighting, 4.2MHz LP, 100kHz HP 400kHz to 100MHz, Input Referred Post I 2C Programming
nV/ Hz
ns
Notes: 1. 100% tested at 25C. 2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch. 3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch. 4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output. 5. SNR = 20 * log (714mV / rms noise).
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
I2C BUS Characteristics
TA = 25C, Vcc = 5V unless otherwise noted.
Symbol
Vil Vih fSCL tr tf tlow thigh tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA Note: 1. 100% tested at 25C.
Parameter
Digital Input Low1 Digital Input High Clock Frequency Input Rise Time Input Fall Time Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low to High
1
Conditions
SDA,SCL,ADDR SDA,SCL,ADDR SCL 1.5V to 3V 1.5V to 3V
Min.
0 3.0
Typ.
Max.
1.5 Vcc
Unit
V V kHz ns ns s s ns ns s s s s
100 1000 300 4.7 4.0 300 0 4 4.7 4 4.7
SDA
t BUF t LOW
tf
SCL
tr
t t
t HD,STA
HD,DAT
HIGH
t SU,DAT
SDA
t SU,STA
t SU,STO
Figure 3. I2C Bus Timing
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
I2C Interface
Operation
The I2C-compatible interface conforms to the I2C specification for Standard Mode. Individual addresses may be written, but there is no read capability. The interface consists of two lines: a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply through an external resistor. Data transfer may be initiated only when the bus is not busy. Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line during this time are interpreted as control signals.
SCL
SDA
Data line stable; data valid
Change of data allowed
Figure 4.
Bit Transfer
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as start condition (S). A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as stop condition (P).
SCL
S
P
SDA START condition
Figure 5. START and STOP conditions
STOP condition
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter while the master generates an extra acknowledge-related clock pulse. The slave receiver addressed must generate an acknowledge after the reception of each byte. A master receiver must generate an acknowledge after the reception of each byte clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
START condition
clock pulse for acknowledgement
SCL FROM MASTER
1
2
8
9
DATA OUTPUT BY TRANSMITTER
DATA OUTPUT BY RECEIVER
Figure 6.
Acknowledgement on the I2C Bus start procedure. The I2C bus configuration for a data write to the FMS6502 is shown in Figure 7.
I2C Bus Protocol
Before any data is transmitted on the I2C bus, the device which is to respond is addressed first. The addressing is always carried out with the first byte transmitted after the
1 SCL
9
1
9
SDA
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY FMS6502
D7
D6
D5
D4
D3
D2
D1
D0
START BY MASTER
FRAME1 SERIAL BUS ADDRESS BYTE
ACK. BY FMS6502 FRAME 2 ADDRESS POINTER REGISTER BYTE 9
1 SCL(CONTINUED)
SDA(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY FMS6502 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 7. Write Register Address to Pointer Register; Write Data to Selected Register
3.3V Operation
The FMS6502 operates from a single 3.3V supply. With Vcc = 3.3V, the digital input low (Vil) is 0V to 1V and the digital input high (Vih) is 1.8V to 2.9V.
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Applications Information
Input Clamp / Bias Circuitry
The FMS6502 can accommodate AC- or DC-coupled inputs. Internal clamping and bias circuitry are provided to support AC-coupled inputs. These are selectable through the CLMP bits via the I2C-compatible interface. For DC-coupled inputs, the device should be programmed to use the 'bias' input configuration. In this configuration, the input is internally biased to 625mV through a 100k resistor. Distortion is optimized with the output levels set between 250mV above ground and 500mV below the power supply. With AC-coupled inputs, the FMS6502 uses a simple clamp rather than a full DC-restore circuit. For video signals with and without sync; (Y,CV,R,G,B), the lowest voltage at the output pins is clamped to approximately 300mV above ground. If symmetric AC-coupled input signals are used (Chroma,Pb,Pr,Cb,Cr), the bias circuit can be used to center them within the input common range. The average DC value at the output is approximately 1.27V. Figure 8 shows the clamp mode input circuit and the internally controlled voltage at the input pin for AC-coupled inputs.
Lowest voltage set to 125mV 0.1F
Output Configuration
The FMS6502 outputs may be AC or DC-coupled. DCcoupled loads can drive a 150 load. AC-coupled outputs are capable of driving a single, doubly terminated video load of 150. An external transistor is needed to drive DC low-impedance loads. DC-coupled outputs should be connected as indicated in Figure 10.
75
FMS6502 Output Amplifier
75
Figure 10. DC-Coupled Load Connection
Configure AC-coupled loads as shown in Figure 11.
220F
FMS6502 Output Amplifier
75
75
Video source must be AC coupled
FMS6502 Input Clamp
75
Figure 11. AC-Coupled Load Connection
Figure 8. Clamp Mode Input Circuit
Figure 9 shows the bias mode input circuit and the internally controlled voltage at the input pin for AC-coupled inputs.
Average voltage set to 625mV 0.1F
When an output channel is not connected to an input, the input to that particular channel's amplifier is forced to approximately 150mV. The output amplifier is still active unless specifically disabled by the I2C interface. Voltage output levels depend on the programmed gain for that channel.
Driving Capacitive Loads
FMS6502 Input Bias
When driving capacitive loads, use a 10-series resistance to buffer the output, as indicated in Figure 12.
10
CL
Video source must be AC coupled
75
FMS6502 Output Amplifier
Figure 9. Bias Mode Input Circuit
Figure 12. Driving Capacitive Loads
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Crosstalk
Crosstalk is an important consideration when using the FMS6502. Input and output crosstalk represent the two major coupling modes that may be present in a typical application. Input crosstalk is crosstalk in the input pins and switches when the interfering signal drives an open switch. It is dominated by inductive coupling in the package lead frame between adjacent leads. It decreases rapidly as the interfering signal moves further away from the pin adjacent to the input signal selected. Output crosstalk is coupling from one driven output to another active output. It decreases with increasing load impedance as it is caused mainly by ground and power coupling between output amplifiers. If a signal is driving an open switch, its crosstalk is mainly input crosstalk. If it is driving a load through an active output, its crosstalk is mainly output crosstalk. Input and output crosstalk measurements are performed with the test configuration shown in Figure 13. Crosstalk from multiple sources into a given channel is measured with the setup shown in Figure 14. Input In1 is driven with a 1Vpp pulse source and connected to outputs Out1 to Out8. Input In9 is driven with a secondary, asynchronous gray field video signal and is connected to Out9. All other inputs are AC terminated with 75. Crosstalk effects on the gray field are measured and calculated with respect to a standard 1Vpp output measured at the load. If not all inputs and outputs are needed, avoid using adjacent channels to reduce crosstalk.
TERMINATION IN1
Bias
TERMINATION Bias IN1 IN2 - IN8 are AC-Term to Ground w/75 IN1 = 1VPP Open switch for input crosstalk. Close switch for output crosstalk.
IN1 driven with SD video 1VPP. IN6 driven with asynchronous SD video 1VPP. IN2,3,4,5,7,8 are AC-term to GND with 75 .
IN6
Bias
IN8
Bias
Measure crosstalk from channels 1-5 into channel 6 OUT1 OUT6
IN8
Bias
Figure 14. Test Configuration for Multi-Channel Crosstalk
Input Crosstalk from IN1 to OUTx OUT1 Output Crosstalk from OUT1 to OUTx OUT6
Gain = 6dB Out1 = 2.0VPP
Figure 13. Test Configuration for Crosstalk
For input crosstalk, the switch is open and all inputs are in bias mode. Channel 1 input is driven with a 1Vpp signal, while all other inputs are AC terminated with 75. All outputs are enabled and crosstalk is measured from IN1 to any output. For output crosstalk, the switch is closed. Crosstalk from OUT1 to any output is measured.
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Layout Considerations
General layout and supply bypassing play a major role in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board to guide layout and aid device evaluation. The demo board is a fourlayer board with full power and ground planes. Following this layout configuration provides optimum performance and thermal characteristics for the device. For the best results, follow the steps and recommended routing rules listed below. * Make the PCB as thin as possible by reducing FR4 thickness. * Use vias in power pad to tie adjacent layers together. * Remember that baseline temperature is a function of board area, not copper thickness. * Modeling techniques can provide a first-order approximation.
Recommended Routing/Layout Rules
* Do not run analog and digital signals in parallel. * Use separate analog and digital power planes to supply power. * Traces should run on top of the ground plane at all times. * No trace should run over ground/power splits. * Avoid routing at 90-degree angles. * Minimize clock and video data trace length differences. * Include 10F and 0.1F ceramic power supply bypass capacitors. * Place the 0.1F capacitor within 0.1 inches of the device power pin. * Place the 10F capacitor within 0.75 inches of the device power pin. * For multilayer boards, use a large ground plane to help dissipate heat. * For two-layer boards, use a ground plane that extends beyond the device body by at least 0.5 inches on all sides. Include a metal paddle under the device on the top layer. * Minimize all trace lengths to reduce series inductance.
Power Dissipation
Worst-case, additional die power due to DC loading can be estimated at Vcc2/4Rload per output channel. This assumes a constant DC output voltage of Vcc/2. For 5V Vcc with a dual DC video load, add 25/(4*75) = 83mW, per channel.
Applications for the FMS6502 Video Switch Matrix
The increased demand for consumer multimedia systems has created a large challenge for system designers to provide cost-effective solutions to capitalize on the growth potential in graphics display technologies. These applications require cost-effective video switching and filtering solutions to deploy high-quality display technologies rapidly and effectively to the target audience. Areas of specific interest include HDTV, media centers, and automotive infotainment (such as navigation, in-cabin entertainment, and back-up cameras). In all cases, the advantages the integrated video switch matrix provides are high-quality video switching specific to the application, as well as video input clamps and on-chip, lowimpedance output cable drivers with switchable gain. Generally the largest application for a video switch is for the front-end of an HDTV. This is used to take multiple inputs and route them to their appropriate signal paths (main picture and picture-in-picture, or PiP). These are normally routed into ADCs that are followed by decoders. Technologies for HDTV include LCD, plasma, and CRT, which have similar analog switching circuitry.
Thermal Considerations
Since the interior of most systems, such as set-top boxes, TVs, and DVD players, are at +70C; consideration must be given to providing an adequate heat sink for the device package for maximum heat dissipation. When designing a system board, determine how much power each device dissipates. Ensure that devices of high power are not placed in the same location, such as directly above (top plane) or below (bottom plane) each other on the PCB.
VIPDEMOTM Control Software
The FMS6502 is configured via an I2C-compatible digital interface. To facilitate demonstration, Fairchild Semiconductor had developed the VIPDEMOTM GUI-based control software to write to the FMS6502 register map. This software is included in the FMS6502DEMO kit. A parallel port I2C adapter and an interface cable to connect to the demo board are also included. Besides using the full FMS6502 interface, the VIPDEMOTM can also be used to control single register read and writes for I2C.
PCB Thermal Layout Considerations
* Understand the system power requirements and environmental conditions. * Maximize thermal performance of the PCB. * Consider using 70m of copper for high-power designs.
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
www.fairchildsemi.com 11
FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 15. 24-Lead Thin Shrink Small Outline Package
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
www.fairchildsemi.com 12
FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
www.fairchildsemi.com
(c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0
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